Freescale Semiconductor /MK61F15 /DDR /CR27

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CR27

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)PLEN 0 (0)PRIEN 0 (0)RWEN 0 (0)SWPEN

SWPEN=0, RWEN=0, PRIEN=0, PLEN=0

Description

DDR Control Register 27

Fields

PLEN

Placement Enable

0 (0): Disabled. The command queue is a straight FIFO.

1 (1): Enabled. The command queue is filled according to the placement logic factors.

PRIEN

Priority Enable

0 (0): Disabled

1 (1): Enabled

RWEN

Read Write same Enable

0 (0): Disabled

1 (1): Enabled

SWPEN

Swap Enable

0 (0): Disabled

1 (1): Enabled

Links

() ()